The invention relates to a semiconductor device and a method for making the same, and more particularly to a semiconductor device with trench capacitors and stack capacitors and a method for fabricating the same.
Without limiting the scope of the invention, its background is described in connection with semiconductor devices and dynamic random access memory (DRAM) cells as examples.
It has been the trend to scale down the size of memory cells to increase the integration level and thus to increase the memory size of DRAM chips. As the size of memory cell is reduced, the capacity of the capacitor used in the memory cell is correspondingly reduced.
A memory cell of DRAM topically consists of a storage capacitor and an access transistor. Digital information is stored in the capacitor and accessed through the transistor, by way of addressing the desired memory cell via interlaced bit lines and word lines. In order to construct high density DRAMs in a reasonably sized chip area, both the transistor and capacitor elements must occupy less lateral space in each memory cell than in the previous generation DRAM designs. As DRAMs are scaled down there is a continuous challenge to maintain a sufficiently high stored charge in each memory cells. Efforts to increase capacitance without increasing the size of the occupied planar area of the capacitor have been concentrated on building three dimensional capacitor structures, which increase the capacitor surface area. Thus, cell structures have had to change from the conventional planar-type capacitors to either trench capacitors or stack capacitors. With the advent of large-scale integrated DRAM devices, the size of the devices has been continuously reduced such that the available area for a single memory cell has become very small. This causes a reduction in capacitor area, resulting in the reduction of cell capacitance.